EN0-001 試験問題を無料オンラインアクセス

A simple method of measuring the performance of an application is to record the execution time using the clock on the wall or a wristwatch.
When is this method INAPPROPRIATE?

• A.When executing the software using a simulation model
• B.When instruction tracing is enabled
• C.When the processor is not executing instructions from cache
• D.When the processor is a Cortex-R4

Consider the following code sequence, executing on a processor which implements ARM Architecture v7-A.
LDR r0, [r1]
STR r0, [r2]
STR r3, [r3]
R1 points to a location in normal memory. R2 and R3 point to device memory.
Which of the following statements best describes the ordering rules which apply to this sequence?

• A.The two writes to device memory will happen in program order, but the read can be performed out of order
• B.The memory accesses can happen in any order
• C.The memory accesses will happen in program order
• D.The read to r0 and the write from r0 will happen in program order, but the write from r3 can be performed out of order

A 32KB 4-way set associative instruction cache supports a cache line size of 64 bytes. How many bits are required to index a cache line in a way?

• A.6 bits
• B.7 bits
• C.15 bits
• D.9 bits

On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?

• A.This transition is not possible
• B.Execution of an SMC instruction followed by an SVC instruction
• C.Execution of an SVC instruction followed by an SMC instruction
• D.Execution of an SMC instruction

Assume a little-endian system.
What is the value of R5 after the execution of the following piece of code?

• A.0x102
• B.0xBB
• C.0xAABBCC22
• D.0xCC